library ieee;
use ieee.std_logic_1164.all;
entity adder1 is 
port (a,b,cin:in std_logic;
		sum,cout:out std_logic
);
end entity adder1;

architecture bool of adder1 is
begin
sum <= a xor b xor cin;
cout <= (a and b)or(b and cin)or(a and cin);
end architecture bool;


